Ultra-Small Device Engineering Laboratory

 Publications

2012

  1. M. Miyake, J. Nakashima, M. Miura-Mattausch, “Reverse-Recovery-Effect Modeling for p-i-n Diodes”, The 9th International Workshop on Compact Modeling, pp. 25-28, Sydney, 2012. 02
  2. A. Toda, Y. Fukunaga, M. Miyake, H. Kikuchihara, M. Miura-Mattausch, “Transient History-Effect in SOI-MOSFETs and its Compact Modeling”, The 9th International Workshop on Compact Modeling, pp.29-32, Sydney, 2012. 02
  3. C. Ma, H. J. Mattausch, M. Miyake, K. Matsuzawa, T. Iizuka, S. Yamaguchi, T. Hoshida, A. Kinoshita, T. Arawaka, J. He, M. Miura-Mattausch., “Unified Reaction-Diffusion Model for Accurate Prediction of Negative Bias Temperature Instability Effect”., Jpn. J. Appl. Phys., Vol. 51, No.2, 02BC07, 2012.02.
  4. 三好俊輝、三浦道子、“高耐圧デバイスにおけるImpact Ionization Currentのモデル化”、第59回応用物理学会、早稲田大学(ポスター)、2012.03.
  5. K. Ishiguro, A. Ueno, A. Toda, M. Miyake, H.J. Mattausch, M. Miura-Mattausch, “Compact Thermal-Interaction Model for Dynamic within Chip Temperature Determination by Circuit Simulation,” 2012
    International Conference on Microelectronic Test Structure, San Diego, 2012.03.
  6. S. Emoto, T. Miyoshi, M. Miyake, H.J. Mattausch, M. Miura-Mattausch, T. Iizuka, Y. Sahara, T. Hoshida, K. Matsuzawa, T. Arakawa, “Experimental Extraction of Substrate-Noise Couping between MOSFETs and its Compact Modeling for Circuit Simulation,” 2012 International Conference on Microelectronic Test Structure, San Diego, 2012.03.
  7. M. Miura-Mattausch, “Surface Potential Based Modeling: HiSIM Compact Model Family”. MOS Modeling and Parameter Extraction Working Group MOS-AK/GSA Workshop, Noida, 2012. 03 (invited)

2011

  1. H. J. Mattaush, A. Yumisaki, A. Kaya, T. Koide, M. Miura-Mattausch, “Application of Surface-Potential Morel HiSIM2 to Variation Analysis of CMOS Technologies”, The 8th International Workshop on Compact Modeling, pp. 21-26, Yokohama, 2011. 01
  2. M. Miyake, T. Kajiwara, H. Kikuchihara, U. Feldmann, H. J. Mattausch, M. Miura-Mattausch, “Modeling of Local Self-Heating Effect and Effective Temperature for Device Characteristics”, The 8th International Workshop on Compact Modeling, pp. 59-63, Yokohama, 2011. 01
  3. N. Sadachika, S. Mimura, A. Yumisaki, K. Johguchi, A. Kaya, M. Miura-Mattausch, H. J. Mattausch, “Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design”, IEICE Trans. Electronics, Vol. E94-C, No. 3, pp361-367, Tokyo, 2011.03.
  4. S. Amakawa, A. Toda, K. Ohyama, N. Higashiguchi, D. Hori, Y. Shintaku, M. Miyake, M. Miura-Mattausch, “Universal Relationship between Substrate Current and History Effect in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors”, Vol. 50, 04DC12, Jpn. J. Appl. Phys., 2011. 04.
  5. T. Saito, A. Tanaka, T. Hayashi, H. Kikuchihara, T. Kanamoto, H. Masuda, M. Miyake, S. Amakawa, H.J. Mattausch, M. Miura-Mattausch, “Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics”, Vol. 50, 04DP03, Jpn. J. Appl. Phys., 2011. 04.
  6. 福島賢治、田中昭洋、三浦道子、“Trench-Gate型高圧MOSFETの為の回路シュミレーション用ドリフト抵抗モデル”、第58回応用物理学関係連合講演会、神奈川工科大学(ポスター)2011.03.
  7. M. Miura-Mattausch, M. Miyake, H. Kikuchihara, U. Feldmann, H.J. Mattausch, “Complete Surface-Potential Modeling Approach mplemented in the HiSIM Compact Model Family for Any MOSFET Type”. NSTI-Nanotech 2011, pp. 706-709, Boston, 2011. 06.
    (Invited)
  8. Y. Shintaku, H. Ichimiya, M. Miura-Mattausch, K. Endo, S, O’uchi, M. Masahara, “HiSIM-DG for Extracting Statistical Variations of Measured I-V Characteristics”, NSTI-Nanotech 2011, pp. 772-775, Boston, 2011. 06.
  9. A. Tanaka, K. Fukushima, T. Sakuta, H. Kikuchihara, M. Miyake, H.J. Mattausch, M. Miura-Mattausch, “Modeling of the Impurity-Gradient Effect in High-Voltage MOSFETs”, NSTI-Nanotech 2011, pp. 780-783, Boston, 2011. 06.
  10. A. Tanaka, Y. Oritsuki, H. Kikuchihara, M. Miyake, H.J. Mattausch, M. Miura-Mattausch, Y. Liu, K. Green, “Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS Devices”. IEEE Trasactions on Electron Devices, Vol. 58, pp. 2072-2080, 2011. 07.
  11. H.J. Mattausch, A. Yumisaki, A. Kaya, T. Koide, M. Miura-Mattausch, “Analysis and Prediction of Device and Circuit Variations with the Compact Surface-Potential Model HiSIM2”, International Conference on Materials for Advanced Technologies(ICMAT2011), Symposium on Reliability and Variability of Emerging Devices for Future Technologies and USLI Circuits and Systems, Singapore, 2011. 06.
  12. T. Nakahagi, D. Sugiyama, S. Yukuta, M. Miyake, M. Miura-Mattausch, S. Miyano., “Modeling of Enhanced 1/f Noise in TFT with Trap Charges” 2011 International Conference on Simulation of Semiconductor Processes and Devices, pp.171-174, Osaka, 2011. 09 (Poster).
  13. M. Miyake, S. Kusu, H. Kikuchihara, A. Tanaka, Y. Shintaku, M. Ueno, J. Nakashima, U. Feldmann, T. Yoshida., “The Flexible Compact SOI-MOSFET Model HiSIM-SOI Valid for Any Structural Types”, 2011 International Conference on Simulation of Semiconductor Processes and Devices, Osaka, 2011. 09.
  14. J. Nakashima., M. Miyake, M. Miura-Mattausch., “Dynamic-Carrier-Distribution-Based Compact Modeling of P-i-N Diode Reverse ecovery Effect”, the 2011 International Conference on Solid State Devices and Materials, pp.1379-1380, Nagoya, 2011. 09.
  15. C. Ma, M. Miyake, K. Matsuzawa, T. Iizuka, T. Hozhida, A. Kinoshita., T. Arakawa., J. He., M. Miura-Mattausch., “Compact Reaction-Diffusion Model for Accurate NBTI Prediction”.,  the 2011 International Conference on Solid State Devices and Materials, Nagoya, 2011. 09. 

2010

  1. K. Ishimura, S. Kusu and M. Miura-Mattausch, “Compact model HiSIM-DG valid for independent DG-MOSFETs structures”, The 7th International Workshop on Compact Modeling, pp. 20-22, Taipei, 2010.1
  2. Y. Shintaku, S. Kusu, G. Suzuki, K. Konno and M. Miura-Mattausch, “Modeling of current for high performance optoelectric circuit”, The 7th International Workshop on Compact Modeling, pp. 48-51, Taipei, 2010.1
  3. M. Miura-Mattausch, “Origin of Advanced MOSFET Characteristics Important for Circuit Design,” International Conference on Microelectronic Test Structures, Tutorial, Hiroshima, 2010. 4.(Invited)
  4. 三浦道子、宮野壮一郎、大杉大介、行田昌平、新宅康弘、三宅正尭、天川修平、“TFT特性におけるトラップ電荷の影響とHiSIMにおけるこのモデル化”、薄膜材料デバイス研究会、Nara, 2010.11.(invited)
  5. Y. Orituki, M. Yokomichi, T. Kajiwara, A. Tanaka, N. Sadachika, M. Miyake, H. Kichchibara, K. Johguchi, U, Feldmann, H. J. Mattausch, M. Miura-Mattausch, “HiSIM-HV: A Compact Model for Simulation of High-Voltage MOSFET Circuits”, IEEE Transactions on Electron Devices, Vol. 57, No. 10, pp. 2671-2678, 2010.10.
  6. 241. A. Tanaka, Y. Oritsuki, H. Kikuchibara, M. Miyake, H. J. Mattausch, M. Miura-Mattausch, Y. Liu, K. Green,“Modeling of 2D Bais Control in Overlap Region of High-Voltage MOSFETs for Accurate Device/Circuit Performance Prediction”, pp. 243-246, Bologna, SISPAD 2010

2009

  1. S. Kusu, K. Ishimura, K. Ohyama, T. Miyoshi, N. Sadachika, T. Murakami, M. Ando, H. J. Mattausch, M. Miura-Mattausch,”HiSIM-SOI: A Dynamic Depletion Model Valid for Device and Circuit Optimaization,” pp. 13-16, The 6th International Workshop on Comapact Modeling, Yokohama, 2009.1.
  2. T. Kojima, T. Kajiwara, M. Miyake, U. Feldmann, M. Miura-Mattausch, “Electro-thermal Simulation for Automotive Power Application using Novel LDMOS Model,” pp.67-70, The 6th International Workshop on Comapact Modeling, Yokohama, 2009.1.
  3. T. Miyoshi, S. Kusu, T. Minami, M. Miyake, N. Sadachika, H. J. Mattausch, M. Miura-Mattausch, “Analysis and Modeling of p-i-n Photodiode Noise,” pp. 71-74, The 6th International Workshop on Comapact Modeling, Yokohama, 2009.1.
  4. T. Kajiwara, M. Miyake, N. Sadachika, H. Kikuchihara, U. Feldmann, H. Mattausch, M. Miura-Mattausch, “Spatial Distribution Analysis of Self-Heating Effect in High-Voltage MOSFETs,” The IEEE Applied Power Electronics Conference and Exposition, pp. 1687-1691, Washington, 2009.2.
  5. 三浦道子、貞近倫夫、折附泰典、作田隆、三宅正尭、横道政宏、梶原隆宏、菊地原秀行、Uwe Feldmann、Hans Juergen Mattausch, “高耐圧MOSFET特性のモデル化と回路シュミレータへの組み込み“, pp. 37-41, 第22回回路とシステム軽井沢ワークショップ, 軽井沢,2009.4.(invited)
  6. K. Ishimura, N. Sadachika, M. Miura-Mattausch, “Modeling of Subthreshold Swing and Analysis of Short-Channel Effects in Double-Gate Metal Oxide Semiconductor Field-Effect Transistors”, Jpn. J. Appl. Phy., vol.48, No.4, 04C054, 2009.4.
  7. N. Sadachika, S. Kusu, K. Ishimura, T. Murakami, T. Kajiwara, T. Hayashi, Y. Nishikawa, T. Yoshida, and M. Miura-Mattausch, “HiSIM-SOI: SOI-MOSFET Model for Circuit Simulation Valid also for Device Optimization,” NSTI-Nanotech, pp. 550-553, Houston, 2009.5. (invited)
  8. K. Ishimura, N. Sadachika, S. Kusu, M. Miura-Mattausch, “Compact Model HiSIM-DG both for Symmetrical and Asymmetrical DG-MOSFET Structures,” NSTI-Nanotech, pp. 584-587, Houston, 2009.5.
  9. Y. Oritsuki, N. Sadachika, M. Miyake, T. Kajiwara, T. Sakuda, H. Kikuchihara, U. Feldmann, H. J. Mattausch, M. Miura-Mattausch, “High-Voltage MOSFET Model Valid for Device Optimization,” NSTI-Nanotech, pp. 600-603, Houston, 2009.5.
  10. M. Miyake, D. Hori, N. Sadachika, U. Feldmann, M. Miura-Mattausch, H. J. Mattausch, T. Iizuka, K. Matsuzawa, Y. Sahara, T. Hoshida, T. Tsukada,”Non-Quasi-Static Carrier Dynamics of MOSFETs Low-Voltage Operation”, IEICE Trans. Electron., Vol. E92-C, No. 5, pp. 608-615, 2009.5.
  11. M. Miyake, D. Hori, N. Sadachika, U. Feldmann, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Miyamoto,”Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors”, IEICE Trans. Electron., Vol. E92-C, No. 6, pp. 777-784, 2009.6.
  12. M. Miura-Mattausch, “回路設計用設計MOSFETモデルの進化―Meyerモデルから表面ポテンシャルモデルへの推移―”, IEEE Fundamentals Review, Vol. 3, No. 1, pp. 57-65, 2009.7.
  13. H. J. Mattausch, N. Sadachika, A. Yumisaki, A. Kaya, W. Imafuku, K. Johguchi, T. Koide, M. Miura-Mattausch, ”Correlating Microscopic and Variation With Surface-Potential Compact Model”, IEEE Electron Devices Letters, Vol. 30, No. 8, pp. 873-875, 2009.8.
  14. 新宅泰弘、楠隼太、三好哲平、三浦道子、“p-i-nフォトダイオードにおける光入力応答の測定及びモデル化”、第70回応用物理学会学術講演会、pp. 804, 8p-TB-3, Toyama, 2009.9.
  15. 西川雄也,三宅正尭,貞近倫夫,三浦道子、“Drift-Diffusionを考慮した完全対称モデルの実現”、第70回応用物理学会学術講演会、pp. 805, 8p-TB-4, Toyama, 2009.9.
  16. 行田昌平,杉山大介,東口直矢,宮野壮一郎,三浦道子、“TFTにおけるGrain BoundaryのThermal Noiseへの影響”、第70回応用物理学会学術講演会, pp. 717, 9p-TB-11, Toyama, 2009.9.
  17. 杉山大介,行田昌平,東口直矢,三浦道子、“TFTで特徴的に誘起される1/f noiseの解析”、第70回応用物理学会学術講演会、pp. 718, 9p-TB-12, Toyama, 2009.9.
  18. T. Sakuta, N. Sadachika, Y. Oritauki, M. Miyake, T. Kajiwara, H. kikuchihara, U. Feldmann, H. J. Mattausch, M. Miura-Mattausch, “Effect of Impact-Ionization-Generated Holes on the Breakdown Mechanism in LDMOS Devices,” 2009 International Conference on Simulation of Semiconductor Processes and Devices, pp. 214-217, San Diego, 2009.9.
  19. T. Hayashi, N. Sadachika, T. Murakami, D. Sugiyama, S. Yukuta, S. Kusu, K. Johguchi, M. Miyake, H. J. Mattausch, M. Miura-Mattausch, S. Baba, J. Ida, “Modeling of Electron Tunneling in SOI-MOSFET and Its Influence on Device Characteristics,” 2009 IEEE International SOI Conference, Session 8.5, Foster City, 2009.10.
  20. D. Hori, M. Miyake, N. Sadachika, H. J. Mattausch, M. Miura-Mattausch, T. Iizuka, T. Hoshida, K. Matsuzawa, Y. Sahara, T. Tsukada, “Influence of Carrier Transit Delay on CMOS Switching Performance,” 2009 International Conference on Solid State Devices and Materials, pp. 777-778, Sendai, 2009.10.
  21. Y. Shintaku, S. Kusu, T. Miyoshi, M. Miyake, N. Sadachika, K. Konno, G. Suzuki, M. Miura-Mattausch, “Accurate Prediction of Photocurrent Response for High Performance Optoelectric Circuit Simulatio,” 2009 International Conference on Solid State Devices and Materials, pp. 1296-1297, Sendai, 2009.10.
  22. K. Johguchi, A. Kaya, S. Izumi, H. J. Mattausch, T. Koide, N. Sadachika, “Within-Die/Wafer Variation Analysis of Basic CMOS Circuits Based on Surface-Potential-Model HiSIM2,” 2009 International Conference on Solid State Devices and Materials, pp. 1072-1073, Sendai, 2009.10.
  23. 三浦道子、三宅正尭、上口光、楠隼太、石村健太、菊地原秀行、Feldmann Uwe、Mattausch Hans Juergen, “MOSFETコンパクトモデルと今後の展開―バルクMOSFETからマルチゲートMOSFETに向けて―”, (社)電子情報通信学会信学技報, Vol. 109, No. 278, SDM2009-135, pp. 2-7, Tokyo, 2009.11. (Invited)
  24. 三宅正尭、舛岡弘基、ウヴェフェルドマン、三浦道子, “回路シミュレーション用IGBTモデル”HiSIM-IGBT””, (社)電子情報通信学会信学技報, Vol. 109, No. 278, SDM2009-139, pp. 23-27, Tokyo, 2009.11.

2008

  1. M. Miura-Mattausch, H. J. Mattausch, M. Chan, J. He, H. Koike, T. Nakagawa, Y. J. Park, Z. Yu, T. Tsutsumi, “Construction of a Compact Modeling Platform and Its Application to the Development of Multi-Gate MOSFET Models for Circuit Simulation,” The 5th International Workshop on Compact modeling, pp. 1-4, Seoul, 2008.1.(Invited)
  2. M. Yokomichi, N. Sadachika, M. Miyake, T. Kajiwara, Y. Oritsuki, T. Sakuda, U. Feldmann, H.J. Mattausch, and M. Miura-Mattausch, “High-Voltage MOSFET Model with Consistently Determined Potential Distribution in MOS Channel and Drift Region,” The 5th International Workshop on Compact modeling, pp. 49-52, Seoul, 2008.1.
  3. A. Oohashi, M. Miyake, M. Yokomichi, H. Masuoka, T. Kajiwara, T. Kojima, N. Sadachika, U. Feldmann, H.J. Mattausch, and M. Miura-Mattausch, ” Toward Predictable IGBT Model for Optimization of Device Parameters,” The 5th International Workshop on Compact modeling, pp. 53-55, Seoul, 2008.1.
  4. 貞近倫夫, 岡秀樹,田辺亮, 村上貴洋, マタウシュハンスユルゲン, 三浦道子, ”ダブルゲートMOSFETの回路シミュレーション用コンパクトモデル,” 第55回応用物理学関係連合講演会、27p-ZC-4,船橋,2008.3.(Oral)
  5. M. Yokomichi, N. Sadachika, M. Miyake, T. Kajiwara, H. J. Mattausch, M. Miura-Mattausch, “Laterally Diffused Metal Oxide Semiconductor Model for Device and Circuit Optimization,” Jpn. J. Appl. Phys., Vol. 47, No. 4, pp. 2560-2563, 2008. 4.
  6. T. Murakami, M. Ando, N. Sadachika, T. Yoshida, M. Mitiko-Mattausch, “Modeling of Floating-Body Effect in Silicon-on-Insulator Metal-Oxide-Silicon Field-Effect Transistor with Complete Surface-Potential-Based Description,” Jpn. J. Appl. Phys., Vol. 47, No. 4, pp. 2556-2559, 2008. 4.
  7. T. Minami, Y. Takeda, M. Miyake, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Miyamoto, “Frequency Dependence of Measured Metal Oxide Semiconductor Field-Effect Transistor Distortion Characteristic,” Jpn. J. Appl. Phys., Vol. 47, No.4, pp. 2610-2615, 2008. 4.
  8. N. Sadatika, T. Murakami, M. Ando, K. Ishimura, K. Ohyama, M. Miyake, H. J. Mattausch, S. Baba, H. Oka, M. Miura-Mattausch, “Modeling of Floating-Body Devices Based on Complete Potential Description,” NSTI-Nanotech, pp. 778-781, Boston, 2008.6.
  9. Y. Oritsuki, M. Yokomichi, T. Sakuda, M. Miyake, T. Kajiwara, H. Kikuchihara, T. Yoshida, U. Feldmann, H. J. Mattausch, M. Miura-Mattaush, “HiSIM-LDMOS/ HV: A Complete Surface-Potential-Based MOSFET Model for High Voltage Applications,” NSTI-Nanotech, pp. 893-896, Boston, 2008.6.
  10. M. Miura-Mattausch, M. Chan, J. He, H. Koike, H. J. Mattausch, T. Nakagawa, Y. J. Park, T. Tsutsumi, Z. Yu, ”Construction of a Compact Modeling Platform and Its Application to the Development of Multi-Gate MOSFET Models for Circuit Simulation,” NSTI-Nanotech, pp. 764-769, Boston, 2008.6.(invited)
  11. M. Miyake, A. Ohashi, M. Yokomichi, H. Masuoka, T. Kajiwara, N. Sadachika, U. Feldmann, H. J. Mattausch, M.Miura-Mattausch, T. Kojima, T. Shoji, Y. Nishibe, “A Consistently Potential Distribution Oriented Compact IGBT Model,” Power Electronics Specialists Conference, pp. 998-1003, Rhodes, 2008. 6.
  12. H. J. Mattausch, M. Chan, J. He, H. Koike, M. Miura-Mattausch, T. Nakagawa, Y. J. Park, T. Tsutsumi, Z. Yu, “Development of Multi-gate MOSFET Models for Circuit Simulation with a Compact Modeling Platform,” 16th International Conference Mixed Design of Integrated Circuits and Systems, pp. 59-64, Poznań, 2008.6.
  13. H. J. Mattausch, M. Miura-Mattausch, N. Sadachika, M. Miyake, D. Navarro, “The HiSIM Compact Model Family for Integrated Devices Containing a Surface-potential MOSFET Core,” pp.39-50, 16th International Conference Mixed Design of Integrated Circuits and Systems, Poznań, 2008.6.(Plenary)
  14. N. Sadachika, T. Murakami, H. Oka, R. Tanabe, H. J. Mattausch, M. Miura-Mattausch, “Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit Optimization,” IEICE Trans. Electron, E91-C, pp. 1379-1381, 2008.8.
  15. H. Kikuchihara, T. Nakagawa, H. Koike, M. Miura-Mattausch, “Development of Common Platform with Modularized Models Enabling Selective Combinations of Different Models,” IEEE Workshop on Compact Modeling, pp. 67-71, Hakone, 2008.9.
  16. M. Miyake, D. Hori, N. Sadachika, U. Feldmann, M. Miura-Mattausch, H. J. Mattausch, T. Iizuka, K. Matauzawa, Y. Sahara, T. Hoshida, T. Tsukada, “Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation,” International Conference on Simulation of Semiconductor Processes and Devices, pp381-384, Hakone, 2008.9.
  17. S. Miyano, Y. Shimizu, T. Murakami, M. Miura-Mattausch, “A Surface Potential Based Poly-Si TFT Model for Circuit Simulation”, International Conference on Simulation of Semiconductor Processes and Devices, pp373-376, Hakone, 2008.9.
  18. K. Ishimura, N. Sadachika, M. Miura-Mattausch, ”Modeling Analysis of Short-Channel Effects in Double-Gate MOSFETs” International Conference on Solid State Devices and Materials, pp. 46-47, Tsukuba, 2008. 9.
  19. M. Miura-Mattausch, M. Yokomichi, N. Sadachika, Y. Oritsuki, T. Sakuda, M. Miyake, T. Kajiwara, H. Kikuchihara, U. Feldmann, H. J. Mattausch, “Modeling of High-Voltage MOSFETs for Device/ Circuit Optimization,” pp. 730-731, International Conference on Solid State Devices and Materials, Tsukuba, 2008.9. (invited)
  20. T. Kojima, T. Kajiwara, M. Miyake. U. Feldmann, M. Miura-Mattausch, “Capability of Electrothermal Simulation for Automotive Power Application using Novel LDMOS Model,” pp. 734-735, International Conference on Solid State Devices and Materials, Tsukuba, 2008.9.
  21. U. Feldmann, M. Miyake, T. Kajiwara, M. Miura-Mattausch, "On Local Handling of Inner Equations in Compact Models", Proc. on Scientific Computing in Elec. Eng. (SCEE), Espoo, Finland, 2008. 9.
  22. H. J. Mattausch, T. Kajiwara, M. Yokomichi, T. Sakuda, Y. Oritsuki, M. Miyake, N. Sadachika, H. Kikuchihara, U. Feldmann, M. Miura Mattausch, “HiSIM-HV: A Compact Model for Simulation of High-Voltage-MOSFET Circuits,” B1. 5, The 9th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, 2008.10. (invited)
  23. S. Kusu, K. Ishimura, K. Ohyama, T. Miyoshi, D. Hori, N. Sadachika, T. Murakami, M. Ando, H.J. Mattausch, M. Miura-Mattausch, S. Baba, J. Ida, “Consistent Dynamic Depletion Model of SOI-MOSFETs for Device/Circuit Optimization,” P6.2, SOI Conference, New Paltz, 2008.10.

2007

  1. H. J. Mattausch, N. Sadachika, M. Miyake, D. Navarro, T. Warabino, K. Matsumoto, T. Ezaki, M. Miura-Mattausch, T. Yoshida, R. Inagaki, Y. Furui, S. Hazama, T. Ohguro, T. Iizuka, M. Taguchi, S. Miyamoto, “HiSIM231: Toward Solving the Speed versus Accuracy Crisis in Circuit Simulation,” The 4th Int. Workshop on Compact Modeling, pp. 93-96, Yokohama, 2007. 1.
  2. R. Inagaki, N. Sadachika, D. Navarro, Q. Ngo, C. Y. Yang, M. Miura-Mattausch, Y. Inoue, “A Substrate-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2,” The 4th Int. Workshop on Compact Modeling, pp. 89-92, Yokohama, 2007. 1.
  3. Y. Isobe, K. Hara, D. Navarro, Y. Takeda, T. Ezaki, M. Miura-Mattausch, “Shot Noise Modeling in Metal-Oxide-Semiconductor Field Effect Transistors under Sub-Threshold Condition,” IEICE Trans. Electron., Vol. E90-C, NO. 4, pp. 885-894, 2007.4.
  4. M. Miyake, N. Sadachika, D. Navarro, Y. Mizukane, K. Matsumoto, T. Ezaki, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto, “Suface-Potential-Based Metal-Oxide Silicon-Varactor Model for RF Applications,” Jpn. J. Appl. Phys., Vol. 46, No. 4B, pp. 2091-2095, 2007.4.
  5. M. Miura-Mattausch, N. Sadachika, M. Miyake, D. Navarro, T. Ezaki, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Miyamoto, R. Inagaki, Y. Furui, N. Fudanuki, T. Yoshida, “HiSIM 2.4.0: Advanced MOSFET Model for the 45nm Technology Node and Beyond,” NSTI-Nanotech, pp. 479-484,Santa Clara, 2007.5.(invited)
  6. M. Miyake, N. Sadachika, K. Matsumoto, D. Navarro, T. Ezaki, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Miyamoto, “HiSIM-Varactor: Complete Surface-Potential-Based Model for RF Applications,” NSTI-Nanotech, pp. 621-624, Santa Clara, 2007.5.
  7. H. Oka, R. Tanabe, N. Sadachika, A. Yumisaki, M. Miura-Mattausch, “Suppressed Short-Channel Effect of Double-Gate Metal Oxide Semiconductor Field-Effect Transistor and Its Modeling,” Jpn. J. Appl. Phys., Vol. 46, No. 4B, pp. 2096-2100, 2007.4.
  8. T. Minami, Y. Takeda, M. Miyake, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Miyamoto, “Frequency Dependence of Measured MOSFET Distortion Characterstic,” International Conference on Solid State Devices and Materials, pp. 904-905, Tsukuba, 2007.9.
  9. T. Murakami, M. Ando, N. Sadachika, M. Miura-Mattausch, “Modeling of Floating-Body Effect in SOI-MOSFET with Complete Surface-Potential Description,” International Conference on Solid State Devices and Materials, pp.734-735, Tsukuba, 2007.9.
  10. M. Yokomichi, M. Miyake, T. Kajiwara, N. Sadachika, A. Yumisaki, H. J. Mattausch, “LDMOS Model for Device and Circuit Optimization,” International Conference on Solid State Devices and Materials, pp. 738-739, Tsukuba, 2007.9.
  11. N. Sadachika, H. Oka, R. Tanabe, T. Murakami, H. J. Mattausch, M. Miura-Mattausch, “Compact Double-Gate MOSFET Model Correctly Predicting Volume-Inversion Effects,” International Conference on Simulation of Semiconductor Processes and Devices, pp. 289-292, Vienna, 2007.9.
  12. T. Ezaki, N. Sadachika, D. Navarro, T. Warabino, K. Konno, Y. Isobe, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto, ”Noise Measurement and Modeling in Advanced MOSFETs,” 第20回日本ゆらぎ現象研究会, pp. 22-23, 2007. 9.
  13. 三浦道子, “回路設計のための先端MOSFETモデル ~マイヤーモデルから表面ポテンシャルモデルまで~,“ (社)電子情報通信学会信学技報, Vol. 107, No. 264, CAS2007-50, pp. 93-98, 2007.10. (Invited)
  14. M. Miura-Mattausch, N. Sadachika, M. Miyake, A. Yumisaki, H. J. Mattausch, “Analysis of Technology Variations in Advanced MOSFETs with the Surface-Potential-Based Compact Model HiSIM,” ECS Trans., Vol. 11, No. 6, pp. 29-44, Washington, 2007.10. (Keynote Speech)
  15. 村上貴洋、安藤慎、貞近倫夫、吉田隆樹、三浦道子、“SOI-MOSFETにおける基板浮遊効果のモデル化,”(社)電子情報通信学会信学技報, Vol. 107, No. 298, SDM2007-212, pp. 41-45, 2007. 10.
  16. T. Ezaki, D. Navarro, Y. Takeda, N. Sadachika, G. Suzuki, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto, “Non-quasi-static approach with surface-potenyial-based MOSFET model HiSIM for RF circuit simulations,” Mathematics and Computers in Simulation, Vol. 79, pp. 1096-1106, 2008.12.

2006

  1. M. Miura-Mattausch, D.Navarro, N. Sadachika, G. Suzuki, Y. Takeda, M. Miyake, T. Warabino, Y. Mizukane, K. Machida, R. Inagaki, T. Ezaki, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “HiSIM2: Advanced MOSFET Model for RF-Circuit Simulation,” The 3rd Int. Workshop on Compact Modeling, pp. 57-62, Yokohama, 2006. 1.
  2. K. Machida, D. Navarro, M. Miyake, R. Inagaki, N. Sadachika, T. Ezaki, H. J. Mattausch,and M. Miura-Mattausch, “Efficient Non-Quasi-Static MOSFET Model for both Time-Domain and Frequency-Domain Analysis,” IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, pp. 73-76, San Jose, 2006. 1.
  3. D. Navarro, Y. Takeda, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto, “On the validity of Convetional MOSFET Nolineearity Characterization at RF Switching,” IEEE Microwave and Wireless Components Letters, vol. 16, NO. 3, pp. 125-127, 2006.3
  4. T. Ezaki, D. Navarro, N. Sadachika, G. Suzuki, Y. Takeda, M. Miyake, T. Warabino, Y. Mizukane, K. Machida, R. Inagaki, H. J. Mattausch, M. Miura-Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto, ”MOSFET Model HiSIM2 for RF-Circuit Simulation,” The 19th Workshop o Circuits and Systems in Karuizawa, pp. 57-62, 2006. 4. (invited)
  5. M. Miura-Mattausch, D. Navarro, N. Sadachika, G. Suzuki, Y. Takeda, M. Miyake, T. Warabino, K. Machida, T. Ezaki, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, R. Inagaki, S. Miyamoto, “Adavanced Compact MOSFET Model HiSIM2 Based on Surface Potentials with Minimum Number of Approximation,” NSTI-Nanotech 2006, pp. 638-643, Boston, 2006.5. (invited)
  6. M. Miura-Mattausch, N. Sadachika, D. Navarro, G. Suzuki, Y. Takeda, M. Miyake, T. Warabino, Y. Mizukane, R. Inagaki, T. Ezaki, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto, “HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation,” IEEE Trans. Electron Devices, Vol. 53, No. 9, pp. 1994-2007, 2006.9.(invited)
  7. N. Sadachika, D. Kitamaru, Y. Uetsuji, D. Navarro, M. M. Yusoff, T. Ezaki, H. J. Mattausch, M. Miura-Mattausch, “Completely Surface-Potential-Based Compact Model of the Fully Depleted SOI-MOSFET Including Short-Channel Effects,” IEEE Trans. Electron Devices, Vol. 53, No. 9, pp. 2017-2024, 2006.9.
  8. D. Navarro, Y. Takeda, M. Miyake, N. Nakayama, K. Machida, T. Ezaki, H. J. Mattausch, M. Miura-Mattausch, “A carrier-Transit-Delay-Based Nonquasi-Static MOSFET Model for Circuit Simulation and Its Application Harmonic Distortion Analysis,” IEEE Trans. Electron Devices, Vol. 53, No. 9, pp. 2025-2034, 2006.9.
  9. T. Warabino, M. Miyake, D. Navarro, Y. Takeda, G. Suzuki, T. Ezaki, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto, “Analysis and Compact Modeling of MOSFET High-Frequency Noise,” International Conference on Simulation of Semiconductor Processes and Devices, pp. 158-161, Monterey, 2006.9.
  10. H. Oka, R. Tanabe, N. Sadachika, A. Yumisaki, M. Miura-Mattausch, “Suppressed short-channel effect of DG-MOSFET and its modeling,” International Conference on Solid State Devices and Materials, pp. 1040-1041, Yokohama, 2006.9.
  11. M. Miyake, N. Sadachika, D. Navarro, Y. Mizukane, T. Ezaki, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto, “Surface-Potential-Based MOS-Varactor Model for RF Applications,” International Conference on Solid State Devices and Materials, pp. 1044-1045, Yokohama, 2006.9.
  12. N. Sadachika, D. Kitamaru, Y. Uetsuji, D. Navarro, M. Mohd. Yusoff, T.Ezaki, H. J. Mattausch, M. Miura-Mattausch, S. Baba, “HiSIM-SOI: Complete Surface-Potential-Based Fully-Depleted SOI-MOSFET Model for Circuit Simulation,” The 7th International Conference on Solid-State and Integrated-Circuit Technology, pp. 449-452, Hangzhou, 2006. 10.
  13. T. Ezaki, T. Warabino, M. Miyake, N. Sadachika, D. Navarro, H. J. Mattausch, M. Miura-Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S.Miyamoto, “Noise Modeling Based on Self-Consistent Surface-Potential Description for Advaced MOSFETs aiming at RF Applications,” The 7th International Conference on Solid-State and Integrated-Circuit Technology, pp. 1264-1267, Hangzhou, 2006. 10.(invited)
  14. T. Ezaki, G. Suzuki, K. Konno, O. Matsushima, Y. Mizukane, D. Navarro, M. Miyake, N. Sadachika, H. J. Mattausch, M. Miura-Mattausch, “Physics-Based Photodiode Model Enabling Consistent Opto-Electronic Circuit Simulation”, Int. Electron Device Meeting, pp. 187-190, San Francisco, 2006, 12.
  15. H. J. Mattausch, M. Miyake, T. Yoshida. S. Hazama, D. Navarro, N. Sadachika, T.Ezaki, M. Miura-Mattausch, “HiSIM2 Ciruit Simulation,” IEEE Circuits & Devices Magazine, Vol. 22, No. 5, pp.29-38, 2006. 9/10.

2005

  1. M. Murakawa, M. Miura-Mattausch, T. Higuchi, “Towards Automatic Parameter Extraction for Surface-Potential-Based MOSFET Models with the Genetic Algorithm,” Asia and South Pacific Design Automation Conference, pp. 204-207, Shanghai, 2005.1.
  2. M. Murakawa, M. Miura-Mattausch, S. Mimura, T. Higuchi, “Genetic Algorithm for Reliable Parameter Extraction of Complete Surface-Potential-Based Models,” The 2nd International Workshop on Compact modeling, pp. 7-12, 2005.1.
  3. D. Navarro, N. Nakayama, K. Machida, Y. Takeda, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, and S. Miyamoto, “A Carrier Transit Time Delay-Based Non-Quasi-Static MOSFET Model for RF Circuit Simulation,” The 2nd International Workshop on Compact modeling, pp. 23-27, 2005.1.
  4. S. Matsumoto, H. Ueno, S. Hosokawa, T. Kitamura, M. Miura-Mattausch, H. J. Mattausch, T. Ohguruo,S. Kumashiro, T. Yamaguchi, K. Yamashita, N. Nakayama, “1/f-noise Characteristics in 100nm-MOSFETs and its Modeling for Circuit Simulation,” IEICE Trans. Electron., Vol.E88-C, No.2, pp. 247-254, 2005.2.
  5. K. Konno, O. Matsushima, K. Hara, G. Suzuki, D. Navarro and M. Miura-Mattausch, “Carrier Transport Model for Lateral p-i-n Photodiode in High-Frequency Operation,” Jpn. J. Appl. Phys., Vol. 44, No. 4B, pp. 2584-2585, 2005.4.
  6. D. Navarro, T. Mizoguchi, M. Suetake, K. Hisamitsu, H. Ueno, M. Miura-Mattausch, H. J. Mattausch,S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, “A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential,” IEICE Trans. Electronics, Vol. E88-C, No. 5, pp. 1079-1086, 2005.5.
  7. N. Sadachika, M. Md Yusoff, Y. Uetsuji, M. H. Bhuyan, D. Kitamaru, H. J.Mattausch, M. Miura-Mattausch, L. Weiss, U. Feldmann, S. Baba, “The Surface-Potential-Based Model HiSIM-SOI and its Application to 1/f Noise in Fully-Depleted SOI-MOSFET,” Modeling and Simulation of Microsystems, pp. 155-158, Anaheim, 2005.5.
  8. M. Miura-Mattausch, N. Sadachika, M. Murakawa, S. Mimura, T. Higuchi, K. Itoh, R. Inagaki, and Y. Iguchi, “RF-MOSFET Model-Parameter Extraction with HiSIM,” Modeling and Simulation of Microsystems, pp. 69-74, Anaheim, 2005.5. (invited)
  9. Josef Watts(editor), Colin McAndrew(presenteor), Christian Enz, Carlos Galup-Montoro, Gennady Gildenblat, Chenming Hu, Ronald van Langevelde, Mitiko Miura-Mattausch, Rafael Rios, Chih-Tang Sah, “Advanced Compact Models for MOSFETs,” Modeling and Simulation of Microsystems, pp. 3-12, Anaheim, 2005.5. (invited)
  10. T. Ezaki, D. Navarro, Y. Takeda, N. Sadachika, G. Suzuki, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto, “Non-quasi-static analysis with HiSIM, a complete surface-potential-based MOSFET model,” MIXDES 2005, pp. 923-928, Krakow, 2005.6.(invited)
  11. S. Hosokawa, D. Navarro, M. Miura-Mattausch, and H. J. Mattausch, “Gate-length and drain-voltage dependence of thermal drain noise in advanced metal-oxide-semiconductor-field-effect transistors,” Appl. Phys. Letters, 87, 092104, 2005.8.
  12. ナバロ・ドンディ,中山範明,町田顕,竹田陽一,三浦道子,マタウシュ・ハンス・ユルゲン,大黒達也,飯塚貴弘,田口昌彦,熊代成孝,宮本俊介, “RF回路シミュレーションのためのキャリア走行遅延に基づくNon-Quasi-Static MOFETモデル,” 第52回応用物理学関係連合講演会講演予稿集, pp. 16, 29p-ZD-1, 2005.4.
  13. M. Miura-Mattausch, “MOSFET modeling beyond 100nm technology: Challenges and perspectives,” International Conference on Simulation of Semiconductor Processes and Devices, pp.1-6, Tokyo, 2005.9.(Plenary)
  14. G. Suzuki, K. Konno, D. Navarro, N. Sadachika, Y. Mizukane, O. Matsushima and M. Miura-Mattausch, “Time-Domain-Based modeling of carrier transport in lateral p-i-n photodiode,” International Conference on Simulation of Semiconductor Processes and Devices, pp. 107-110, Tokyo, 2005.9.
  15. Y. Takeda, D. Navarro, S. Chiba, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi,S. Kumashiro, and S. Miyamoto, “MOSFET Harmonic Distortion Analysis up to the Non-Quasi-Static Frequency Regime,” IEEE 2005 CICC, pp. 827-830, San Jose, 2005.9.
  16. T. Ezaki, N. Sadachika, D. Navrro, T. Warabino, K. Konno, Y. Isobe, M.Miura-Mattausch, H. J.Mattausch, T. Ohguri, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto, “Noise Measurement and Modeling in Advaced MOSFETs,” 20th Annual Meeting of Japanese Association for Science, Art and Technology of Fluctuations, pp. 22-23, 2005. 9.(invited)

2004

  1. H. Ueno, S. Matsumoto, S. Hosokawa, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, “Modeling of 1/f Noise with HiSIM for 100nm CMOS Technology,” Proc. On the 1st Intetnational Workshop on Compact Medeling, pp. 18-23. 2004.1.(chair)
  2. M. Miura-Mattausch, “MOSFET Modeling for RF-CMOS Design,” Proc. Asia and South Pacific Design Automation Conference 2004, 6A-1, pp. 482-490. Yokohama, 2004.1.(invited)
  3. K. Konno, O. Matsushima, D. Navarro, and M. Miura-Mattausch, “Limit of validity of the drift-diffusion approximation for simulation of photodiode characteristics,” Appl. Phys. Letters, Vol. 84, No. 8, pp. 1398-1400, 2004.2.
  4. N. Nakayama, D. Navarro, M. Tanaka, H. Ueno, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, S. Kumashiro, M. Taguchi, T. Kage, and S. Miyamoto, “Non-quasi-static model for MOSFET based on carrier-transit delay,” IEEE Electronics Letters, Vol. 40, No. 4, pp. 276-278, 2004.2.
  5. M. Miura-Mattausch, S. Hosokawa, D. Navarro, S. Matsumoto, H. Ueno, H. J. Mattausch, T. Ohguro, T. Iizuka, T. Taguchi, T. Kage, and S. Miyamoto, “Noise Modeling with HiSIM Based on Self-Consistent Surface-Potential Description,” Nanotech 2004 Conference Technical Proc., Vol. 2, pp. 66-69. Boston, 2004.3.(invited)
  6. M. Miura-Mattausch, S. Matsumoto, K. Mizoguchi, D. Miyawaki, H. J. Mattausch, S. Itoh, and K. Morikawa, “Test Circuits for Extracting Sub-100nm MOSFET Technology Variations with the MOSFET model HiSIM,” Proc. IEEE 2004 Int. Conference on Microelectronic Test Structures, Vol. 17, No. 9.1, pp. 267-272, 2004.3. (invited)
  7. O. Matsushima, K. Konno, M. Tanaka, K. Hara, and Miura-Mattausch, “Carrier transport in highly generated carrier concentration,” Semiconductor science and technology, Vol. 19, No. 4, S185-187, 2004.4.
  8. D. Kitamaru, Y. Uetsuji, N. Sadachika, and M. Miura-Mattausch, “Complete Surface-Potential-Based Fully-Depleted Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect-Transistor Model for Circuit Simulation,” Jpn. J. Appl. Phys., Vol. 43, No. 4B, pp. 2166-2169, 2004.
  9. 村川正宏、樋口哲也、和田哲典、小田嘉則、馬場俊祐、遠藤伸裕、三浦道子、芝原健太郎、西謙二、伊藤桂一、“高騰するプロセス開発コストを新しいモデル探索手法で削減,” NIKKEI MICRODEVICES, pp. 51-58, 2004.6.
  10. M. Miura-Mattausch, D. Navarro, Y. Takeda, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Miyamoto, “MOSFET Modeling for RF-Circuit Era,” Proc. of the 11th Int. Conference on Mixed Design of Integrated Circuits and Systems 2004, pp. 62-66, Szczecin, 2004.6. (invited)
  11. N. Sadachika, Y. Uetsuji, D. Kitamaru, H. J. Mattausch, M. Miura-Mattausch, L. Weiss, U. Feldmann, and S. Baba, “Fully-Depleted SOI-MOSFET Model for Circuit Simulation and its Application to 1/f Noise Analysis,” Proc. Int. Conf. Simulation Semiconductor Processes & Devices, pp. 255-258, Munich, 2004.9.
  12. D. Navarro, N. Nakayama, K. Machida, Y. Takeda, S. Chiba, H. Ueno, H. J. Mattausch, M. Miura-Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, and S. Miyamoto, “Modeling for Carrier Transport Dynamics at GHz-Frequencies for RF Circuit-Simulation,” Proc. Int. Conf. Simulation Semiconductor Processes & Devices, pp. 259-262, Munich, 2004.9.
  13. 金野幸吉, 松島理, 原清仁, 鈴木学, ナバロ ドンディ, 三浦道子, “p-i-nフォトダイオードの高周波応答特性のモデル化,” (社)電子情報通信学会信学技報, VLD2004-31, SDM2004-155, pp. 1-4, 2004.9.
  14. M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “MOSFET Modeling for RF-Circuit Simulation,” Proc. of the 2004 Int. Conference on Solid-State and Integrated-Circuit Technology, pp. 1118-1122, Beijing, 2004.10. (invited)
  15. K. Konno, O. Matsushima, D. Navarro, and M. Miura-Mattausch, “High frequency response of p-i-n photodiodes analyzed by an analytical model in Fourier space,” J. Appl. Phys. Vol. 96. No. 7, pp. 3839-3844, 2004.10.
  16. 森戸隆文, 久光一也, 溝口健, 細川智士, 上野弘明, 三浦道子, H. J. Mattausch,, 大黒達也, 田口昌彦, 飯塚貴弘, 宮本俊介, “デバイス特性に基づくMOS-only-R2R-ladder 回路解析,” 第51回応用物理学関係連合講演会, pp. 41, 29p-B-7, 2004.3.
  17. 竹内琢也, 溝口健, Dondee Navarro, 上野弘明, 金野幸吉, 三浦道子, 佐々木守, H. J. Mattausch, 大黒達也, 田口昌彦, 飯塚貴弘, 宮本俊介, “発振回路におけるノイズの影響,” 第51回応用物理学関係連合講演会, pp.42, 29p-B-8, 2004.3.
  18. K. Konno, O. Matsushima, K. Hara, G. Suzuki, D. Navarro, and M. Miura-Mattausch, “Carrier Transport Model for Lateral p-i-n Photodiodes at High-Frequency Operation,” Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials, pp. 946-947, Tokyo, 2004.9
  19. K. Hara, O. Matsushima, G. Suzuki, D. Navarro, K. Konno, Y. Isobe, and M. Miura-Mattausch, “Shot Noise Measurement in p-i-n Diode and Its Analysis,” Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials, pp. 438-439, Tokyo, 2004.9.
  20. M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “MOSFET model HiSIM based on surface-potential description for enabling accurate RF-CMOS design,” J. Semiconductor Technology and Science, Vol. 4, No. 3, pp. 133-140, 2004.9

2003

  1. K. Hisamitusu, H. Ueno, M. Tanaka, D. Kitamaru, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. yamaguchi, K. Yamashita, and N. Nakayama, “Temperature-Independence-Point Properties for 0.1μm-Scale Pocket-Implant Technologies and the Impact on Circuit Design,” Proc. Of Asia and South Pacific Design Automation Conference, pp.179-183, Kitakyusyu, 2003.1.
  2. M. Miura-Mattausch, D. Navarro, H. Ueno, S. Jinbou, H, J. Mattausch, K. Morikawa, S. Itoh, A. Kobayashi, and H. Masuda, “HiSIM: Accurate Charge Modeling Important for RF Era,” Proc. Modeling and Simulation of Microsystems, Vol. 2, pp. 258-261, 2003.2. (invited)
  3. Q. Ngo, D. Navarro, T. Mizoguchi, S. Hosokawa, H. Ueno, M. Miura-Mattausch, and C. Y. Yang, “Gate Current Partitioning in MOSFET Models for Circuit Simulation,” Proc. Modeling and Simulation of Microsystems, Vol. 2, pp. 322-325, 2003.2.
  4. 千葉真吾、三谷聡、久光一也、上野弘明、三浦道子、大黒達也、熊代成孝、森川慶一、増田弘生、田口昌彦、宮本俊介, “HiSIMを用いたMOSFETの高調波歪みの解析 (Analysis of harmonic distortion of MOSFET using HiSIM),” 応用物理学会、シンポジウム、28p-ZL-4, 2003.3.
  5. M. Tanaka, H. Ueno, O. Matsushima, and M. Miura-Mattausch, “High-Electric-Field Electron Transport at Silicon/Silicon-Dioxide Interface Inversion Layer,” Jpn. J. Appl. Phys., Vol. 42, No. 3B, pp. L280-282, 2003.3.
  6. D. Navarro, H. Kawano, K. Hisamitsu, T. Yamaoka, M. Tanaka, H. Ueno, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, “Circuit-Simulation Model of Cgd Changes in Small-Size MOSFETs Due to High Channel-Field Gradients,” IEICE Trans. Electron., Vol. E86-C, No.3, pp. 474-480, 2003.3. (invited)
  7. 三浦道子、名野隆夫、盛健次, “回路シミュレーション技術とMOSFETモデリング (Circuit-simulation technics and MOSFET modeling),” Sipec, 2003.3.
  8. T. Mizoguchi, H. J. Mattausch, H. Ueno, D. Kitamaru, K. Hisamitsu, M. Miura-Mattausch, S. Itoh, and K. Morikawa, “Extraction of Inter- and Intra-Chip Device-Parameter Variations with a Differntial-Amplifier-Stage Test Circuit,” Synthesis And System Integration of Mixed Information technologies(SASIMI) 2003 Proceedings(1-8), pp. 76-82, Hiroshima, 2003.4.
  9. N. Nakayama, H. Ueno, T. Inoue, T. Isa, M. Tanaka, and M. Miura-Mattausch, “A Self-Consistent Non-Quasi Static MOSFET Model for Circuit Simulation Based on Transient Carrier Response,” Jpn. J. Appl. Phys., Vol. 42, No. 4B, pp. 2132-2136, 2003.4.
  10. M. Miura-Mattausch, H. Ueno, H. J. Mattausch, K. Morikawa, S. Itoh, A. Kobayashi, and H. Masuda, “100nm-MOSFET model for circuit simulation: challenges and solutions,” IEICE Trans. Electron., Vol. E86-C,No. 6, pp. 1009-1021, 2003.6. (invited)
  11. S. Ito, K. Morikawa, A. Kobayashi, H. Masuda, S. Fujimoto, T. Mizoguchi, H. Ueno, and M. Miura-Mattausch, “Parameter Exteaction of HiSIM1.1/HiSIM1.2,” JPSJ Symposium Series Vol. 2003, No.11, (DAシンポジウム2003論文集), pp. 247-252. 2003.7.
  12. O. Matsushima, M. Tanaka, H. Ueno, K. Hara, K. Konno, and M. Miura-Mattausch, “Carrier transport in highly generated carrier concentration,” Proc. Int. Conf. Nonequilibrium Carrier Dynamics in Semicnoductors, pp. PTu4-8, 2003.7.
  13. S. Hosokawa, Y. Shiraga, H. Ueno, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, S. Kumashiro, M. Taguchi, H. Masuda, and S. Miyamoto, “Origin of Enhanced Thermal Noise for 100nm-MOSFETs,” Ext. Abs. Int. Conf. Solid-State Devices and Materials, pp. 20-21, Tokyo, 2003.9.
  14. D. Kitamaru, Y. Uetsuji, and M. Miura-Mattausch, “A Complete Surface-Potential-Based SOI-MOSFET Model for Circuit Simulation,” Ext. Abs. Int. Conf. Solid-State Devices and Materials, pp. 622-623, Tokyo, 2003.9.

2002

  1. 山岡貴哲、久光和也、北丸大輔、田中将康、上野弘明、三浦道子、マタウシュ ハンス・ユルゲン、熊代成孝、山口哲哉、山下恭司、中山範明、“MOSFETのpocket不純物がchannel抵抗に及ぼす影響,”第49回応用物理学関係連合講演会講演予稿集、28p-ZC-1, 2002. 3.
  2. 久光一也、溝口健、田中将康、上野弘明、三浦道子、マタウシュ ハンス・ユルゲン、熊代成孝、山口哲哉、山下恭司、中山範明、“CMOSのlow voltage Applicationに向けたリングオシレータの温度依存性解析,” 第49回応用物理学関係連合講演会講演予稿集、28p-ZC-2, 2002. 3.
  3. D. Navarro, M. Tanaka, H. Kawano, H. Ueno, M, Miura-Mattausch, “Gate-Drain Capacitance induced by the Lateral Electric Field along the MOSFET channel,” 第49回応用物理学関係連合講演会講演予稿集, 29p-H-3, 2002. 3.
  4. 田中将康、松島理、上野弘明、三浦道子、“Time-of-Flight測定法を用いたSi-MOSFET反転層内キャリア移動度の解析,” 第49回応用物理学関係連合講演会講演予稿集、29p-H-5, 2002. 3.
  5. T. Okagaki, M. Tanaka, H. Ueno, and M. Miura-Mattausch, “Importance of Ballistic Carriers for the Dynamic Response in Sub-100nm MOSFETs,” IEEE Electron Device Letters, Vol. 23, No. 3, pp. 154-156, 2002.3.
  6. M. Miura-Mattausch, “The 100nm-MOSFET model HiSIM and its extension to RF applications,” Int. Sym. Quality Electronic Design, San Jose, 2002.3. (invited)
  7. H. J. Mattausch, M. Suetake, D. Kitamaru, M. Miura-Mattausch, S. Kumashiro, N. Shigyo, S.Odanaka, and N. Nakayama, “Simple nondestructive extraction of the vertical channel-impurity profile of small-size metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Letters, Vol. 80, No. 16, pp. 2994-2996, 2002.4.
  8. H. Ueno, M. Tanaka, K. Morikawa, T. Takahashi, M. Miura-Mattausch, and Y. Omura, “Origin of transconductance oscillations in silicon-on-insulator metal-oxide-semiconductor field-effect transistors with an ultrathin 6-nm-thick active Si layer,” J. Appl. Phys., Vol. 91, No. 8, pp. 5360-5364, 2002.4.
  9. H. Ueno, M. Tanaka, K. Morikawa, T. Takahashi, M. Miura-Mattausch, and Y. Ohmura, “Evidence of mesoscopic carrier transport in SOI-MOSFETs with ultra-thin active Si-layer,” Physica B, Vol. 314, pp. 367-371, 2002.
  10. M. Miura-Mattausch, H. Ueno, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, “HiSIM: Self-Consistent Surface-Potential MOS-Model Valid Down to Sub-100nm Technologies,” Proc. Modeling and Simulation of Microsystems, pp. 678-681, 2002.4. (Invited)
  11. M. Miura-Mattausch, H. Ueno, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, “Circuit Simulation Models for Coming MOSFET Generations,” IEICE Trans. Fund. Electron. , Vol. E85-A, No. 4, pp. 740-748, 2002.4.
  12. K. Morikawa, H. Ueno, D. Kitamaru, M. Tanaka, T. Okagaki, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, “Quantum Effect in Sub-0.1μm MOSFET with Pocket Technologies and its Relevance for the On-Current Condition,” Jpn. J. Appl. Phys., Vol. 41, No. 4B, pp. 2359-2362, 2002.4.
  13. H. Kawano, M. Nishizawa, S. Matsumoto, S. Mitani, M. Tanaka, N. Nakayama, H. Ueno, M. Miura-Mattausch, and H. J. Mattausch, “A Practical Small-Signal Equivalent Circuit Model for RF-MOSFETs Valid Up to the Cut-Off Frequency,” IEEE Int. Microwave Sym. Digest, pp. 2121-2124, 2002.6.
  14. 三浦道子, 上野弘明, “デバイスモデルと回路シミュレーション (Device model and its applications for circuit simulation),” 応用物理 基礎講座第71巻, 第6巻, pp. 726-730, 2002.6.
  15. S. Jinbou, H. Ueno, H. Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch, and H. J. Mattausch, “Analysis of Non-Quasistatic Contribution to Small-Signal Response for Deep Sub-um MOSFET Technologies,” Ext. Abs. Int. Conf. Solid-State Devices and Materials, pp. 26-27,Nagoya, 2002.9.
  16. N. Nakayama, H. Ueno, T. Isa, M. Tanaka, and M. Miura-Mattausch, “A Self-Consistent Non-Quasi Static MOSFET Model for Circuit Simulation Based on Transient Carrier Response,” Ext. Abs. Int. Conf. Solid-State Devices and Materials, pp. 408-409, Nagoya, 2002.9.
  17. D. Navarro, K. Hisamitsu, T. Yamaoka, M. Tanaka, H. Kawano, H. Ueno, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. nakayama, “Circuit-Simulation Model of Gate-Drain-Capacitance Changes in Small-Size MOSFETs Due to High Channel-Field Gradient,” Proc. Int. Conf. Simulation Semicon. Processes & Devices, pp. 51-54, Kobe, 2002.9.
  18. H. Ueno, S. Jinbou, H. Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch, and H. J. Mattausch, “Drift-Diffusion-Based Modeling of the Non-Quasistatic Small-Signal Response for RF-MOSFET Applications,” Proc. Int. Conf. Simulation Semicon. Processes & Devices, pp. 71-74, Kobe, 2002.9.
  19. 三浦道子、上野弘明, “高速デバイスを用い過渡解析に要求される輸送記述 (Carrier transport descripti on required for transient analysis of RF-Devices),” STARCシンポジウム講演予稿集, pp.39-48, 2002.9.
  20. M. Miura-Mattausch, “HiSIM:MOSFET-model for circuit simulation with self-consistent surface potential,” Fabless-Semiconductor-Association Meeting, San Jose, 2002.9.(invited)
  21. H. Ueno, D. Kitamaru, K. Morikawa, M. Tanaka, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, “Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation,” IEEE Trans. Electron Devices, Vol. 49, No. 10, pp. 1783-1789, 2002.10.
  22. S. Matsumoto, K. Hisamitsu, M. Tanaka, H. Ueno, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka, and N. Nakayama, “Validity of Mobility Universality for Scaled Metal-Oxide-Semiconductor Field-Effect Transistors Down to 100nm Gate Length,” J. Appl. Phys., Vol. 92, No. 9, pp. 5228-5232, 2002.11.
  23. M. Miura-Mattausch, H. Ueno, M. Tanaka, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, “HiSIM: A MOSFET Model for Circuit Simulation Connecting Circuit Performance with Technology,” Tech. Digest Int. Electron Devices Meeting, pp. 109-112, San Francisco, 2002.12. (invited)

2001

  1. H. Ueno, T. Kitamura, S. Matsumoto, T. Okagaki, and M. Miura-Mattausch, “Evidence for an additional noise source modifying conventional 1/f frequency dependence in sub-um metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Letters, Vol. 78, No. 3, pp. 380-382, 2001.1.
  2. D. Miyawaki, S. Matsumoto, H. J. Mattausch, S. Ooshiro, M. Suetake, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, “Correlation Method of Circuit-Performance and Technology Fluctuations for Improved Design Reliability,” Proc. Asis and South Pacific Data Automation Conf., pp. 39-44, Yokohama, 2001.1. (Best Paper Award)
  3. M. Miura-Mattausch, “Circuit Simulation Models for Coming MOSFET Generations,” Proc. The 14th Workshop on Circuits and Systems in Karuizawa, pp. 317-322, 2001.4. (invited)
  4. S. Matsumoto, H. J. Mattausch, S. Ooshiro, Y. Tatsumi, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, N. Nakayama, “Test-Circuit-Based Extraction of Inter- and Intra-Chip MOSFET-Performance Variations for Analog-Design Reliability,” Proc. IEEE Custom Integrated Circuit Conf., pp. 357-360, 2001.5.
  5. H. Ueno, M. Tanaka, K. Morikawa, T. Takahashi, M. Miura-Mattausch, and Y. Ohmura, “Evidence of Mesoscopic Carrier Transport in SOI-MOSFETs with Ultra-Thin Active Si Layer,” Ext. Abs. Int. Conf. Nonequil. Carrier Dynam. Semicon., pp. P2.34, 2001.8.
  6. D. Kitamaru, H. Ueno, K. Morikawa, M. Tanaka, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, “Vth Model for Pocket-Implant MOSFETs for Circuit Simulation,” Proc. Int. Conf. Simulation Semicon. Processes & Devices, pp. 392-395, Athens, 2001.9.
  7. K. Morikawa, H. Ueno, D. Kitamaru, M. Tanaka, T. Okagaki, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, “Enhanced Quantum Effect for Sub-0.1μm Pocket Technologies and its Relevance for the On-Current Condition,” Ext. Abst. Int. Conf. Solid-State Devices and Materials, pp. 384-385, Tokyo, 2001.9.
  8. 河野博昭,西澤学,上野弘明,大城誠和,三浦道子, “MOSFET高周波等価回路についての検証,” (社)電子情報通信学会信学技報, Vol. 101, No. 318, pp. 19-23, 2001.9.
  9. H. J. Mattausch, M. Miura-Mattausch, H. Ueno, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, “HiSIM: The First Complete Drift-Diffusion MOSFET Model for Circuit Simulation,” Proc. Int. Conf. Solid-State & Integrated Circuit Technology, pp. 861-866, 2001.10.(Invited)
  10. M. Miura-Mattausch, M. Suetake, H. J. Mattausch, S. Kumashiro, N. Shigyou, S. Odanaka, and N. Nakayama, “Physical Modeling of the Reverse-Short-Channel Effect for Circuit Simulation,” IEEE Trans. Electron. Devices, Vol. 48, No. 10, pp. 2449-2452, 2001.10.
  11. 上野弘明,三浦道子,マタウシュ ハンス・ユルゲン, “サブ100nmデバイスのパラメタ抽出と等価回路モデル,” 応物分科会, 2001.10.
  12. 三浦道子,上野弘明,高橋哲康, “SOI-MOSFETの特性解析及びこれを用いた回路シミュレーション用モデルの開発,” Annual Report of Science Foundation, No. 15, pp. 77-81, 2001
  13. M. Miura-Mattausch, H. J. Mattausch, N. D. Arora, and C. Y. Yang, “MOSFET Modeling Gets Physical,” IEEE Circuit & Devices, Vol. 17, No. 6, pp. 29-36, 2001. (Invited)
  14. 神保聡,河野博昭,上野弘明,三浦道子, “MOSFETのRF応用に向けたnon-quasistatic効果のYパラメタへの寄与の見積もり”

2000

  1. Y. Tatsumi, S. Nara, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka, N Nakayama, “MOSFETモデル評価用テスト回路(1)-しきい値電圧付近の電流領域の評価-,” 電子情報通信学会総合大会後援論文集, pp. 44, 2000. 3.
  2. S. Nara, Y.Tatsumi, M. Miura-Mattusch, S. Kumashiro, T. Yamaguchi, S. Odanaka, N. Nakayama, “MOSFETモデル評価用テスト回路(2)-入力電圧の微少変化の増幅-,” 電子情報通信学会総合大会後援論文集, pp. 45, 2000. 3.
  3. M. Tanaka, N. Tokida, T. Okagaki, M. Miura-Mattausch, W. Hansch, and H. J. Mattausch ,“High performance of short-channel MOSFETs due to an Elevated central-channel doping,” Proc. Asis and South Pacific Data Automation Conf., pp. 365-370, Yokohama, 2000.1.
  4. T. Ono, M. Miura-Mattausch, H. Baumgaertner, and H. J. Mattausch, “Superstable Neutral Electron Traps in Nonplanar Thermal Oxides on Monocrystalline Silicon,” Appl. Phys. Letters, Vol. 76, No. 16, pp. 2298-2300, 2000.4.
  5. M. Miura-Mattausch, S. Ooshiro, and M. Suetake, “Circuit Simulation Models for Coming MOSFET Generations,” Proc. Int. Conf. Simulation Semicon. Processes & Devices, pp. 106-111, Seattle, 2000. 9. (Invited)
  6. M. Suetake, K. Suematsu, H. Nagakura, M. Miura-Mattausch, and H.J. Mattausch, “HiSIM: A Drift-Diffusion-Based Advanced MOSFET Model for Circuit Simulation with Easy Parameter Extraction,” Proc. Simulation of Semicon. Processes and Devices, pp. 261-264, Seattle, 2000.9.
  7. 岡垣健,田中聖康,上野弘明,三浦道子, “Sub-100nm MOSFETにおけるソース/ドレイン電荷分配に対する弾道輸送キャリアの寄与,” Vol. 100, No. 294, pp. 51-55, 2000. 9.
  8. 三浦道子,岡本吉史,吉増敏彦,増田弘生,松本比呂志,樋口哲也, “パラメータのばらつきに対するロバスト設計,” 基礎・境界ソサエティ大会講演論文集, pp. 394-395, 2000.
  9. 三浦道子, “CMOS デバイスシミュレーションの可能性(総説),” 電子情報通信学会誌, Vol. 83, No. 11, pp. 818-821, 2000.11.

1999

  1. M. Tsuno, M. Tanaka, M. Koh, K. Iwamoto, H. Murakami, K. Shibahara, and M. Miura-Mattausch, “Suppression of reverse-short-channel effect in sub-0.1um n-MOSFETs with Sb S/D Implantation,”  Electronic Letters, Vol. 35, No. 6, pp. 508-509, 1999.3.
  2. O. Prigge, M. Suetake, and M. Miura-Mattausch, “Worst/Best Device and Circuit Performances for MOSFETs Determined from Process Fluctuations,” IEICE Trans. Electron., Vol. E82-C, No. 6, pp. 997-1002, 1999.6.
  3. M. Tsuno, M. Suga, M. Tanaka, K. Shibahara, M. Miura-Mattausch, and M. Hirose, “Physically-Based Threshold Voltage Determination for MOSFET’s of All Gate Lengths,” IEEE Trans. Electron Devices, Vol. 46, No. 7, pp. 1429-1434, 1999.7.
  4. M. Tanaka, T. Okagaki, and M. Miura-Mattausch, “Influence of Electron-Phonon Interaction on Carrier Generation in MOSFETs,” Proc. Nonequ. Carreir Dynam. Semicon., pp.131, 1999.7.
  5. T. Takahashi, M. Miura-Mattausch, and Y. Omura, “Transconductance oscillations in metal-oxide-semiconductor field-effect transistors with thin silicon-on-insulator originated by quantized energy levels,” Appl. Phys. Letters, Vol. 75, No. 10, pp. 1458-1460, 1999.9.
  6. W. Hansch, K. Anil, P. Bieringer, C. Fink, F. Kaesen, I. Eisele, “Channel Engineering for the Reduction of Random-Dopant Placement-Induced Threshold Voltage Fluctuations in Vertical Sub-100nm MOSFETs,” Proc. Europ. Solide State Devices Research Conf., pp. 408-412, 1999.9.
  7. T. Ono, M. Miura-Mattausch, H. Baumgartner, H.J. Mattausch, “Deep neutral oxide traps near midgap at corners of nonplaner MOS-capacitors,” Proc. Solide State Devices and Materials, pp. 532-533, 1999.9.
  8. M. Suetake, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, N. Shigyo, S. Odanaka, and N. Nakayama, “Precise Physical Modeling of the Reverse-Short-Channel Effect for Circuit Simulation,” Proc. Simulation of Semicon. Processes and Devices, pp. 207-210, Kyoto,1999.9.
  9. 三浦道子, “トランジスタモデルのあり方とその実現(招待講演),” Proc. STARC Symposium in Kyoto, pp. 213-220, 1999.9.
  10. M. Tanaka, T. Okagaki, and M. Miura-Mattausch, “Influence of laser intensity on carrier generation in MOSFETs,” Physica B, Vol. 272, pp. 554-557, 1999.12.
  11. T. Nagakura, K. Suematsu, S. Suetake, H. J. Mattausch, M. Miura-Mattausch, S. Kumashiro, T. yamaguchi, S. Odanaka, N. Nakayama, “回路モデルHiSIMにおける移動度のuniversalityの保証,”
  12. K.Suematsu, H. Nagakura, M. Suetake, H. J. Mattausch, S. Kumashiro, T.Yamaguchi, S. Odanaka, N. Nakayama, “MOSFETにおけるPoly-Siゲート空乏化及びSi表面量子効果の回路モデル,”

1998

  1. U. Feldmann, R. Kakoschke, M. Miura-Mattausch, and G. Schraud, “Concurrent Technology, Device, and Circuit Development for EEPROMs,” Proc. Asis and South Pacific Data Automation Conf., pp. 123-128, Yokohama, 1998.2.(Best Paper Award)
  2. M. Tsuno, M. Suga, M. Tanaka, K. Shibahara, M. Miura-Mattausch, and M. Hirose, “Reliable Threshold Voltage Determination for Sub-0.1μm Gate Length MOSFET's,” Proc. Asis South Pacific Design Auto. Conf., pp. 111-116, Yokohama, 1998.2.
  3. T. Takahashi, M. Miura-Mattausch, and Y. Omura, “Origin of Drain-Current Oscillation on Ultra-Thin-SOI n-MOSFET,” Proc. Simulation of Semicon. Processes and Devices, pp. 211-214, Leuven , 1998.9.
  4. M. Tanaka, W. Hansch, M. Miura-Mattausch, and H. J. Mattausch, “On the necessity of an optimized central channel doping for Sufficient Performance of Future Scaled MOSFETs,” International Conference on Solid State Devices and Materials, 1998.9.
  5. T. Takahashi, M. Miura-Mattausch, and Y. Omura, “Understanding Conductance Quantization in Thin SOI MOSFET by Quantized-Energy-Level Simulation,” Proc. Int. Workshop Comp. Electron., pp. 246-249, 1998.10.
  6. M. Koh, K. Iwamoto, W. Mizubayashi, H. Murakami, T. Ono, M. Tsuno, T. Mihara, K. Shibahara, S. Yokoyama, S. Miyazaki, M. Miura-Mattausch, and M. Hirose, “Threshold Voltage Fluctuation Induced by Direct Tunnel Leakage Current Through 1.2-2.8nm Thick Gate Oxides for Scaled MOSFETs,” Tech. Digest International Electron Devices Meeting, pp. 919-922, 1998.12.
  7. M. Tanaka, N. Tokida, W. Hansch, M. Miura-Mattausch, and H. J. Mattausch, “Improved performance of MOSFETs with channel length ≦0.1μm due to an elevated central doping,” International Electron Devices Meeting,1998.

1997

  1. H. Hoeningschmid, M. Miura-Mattausch, O. Prigge, A. Rahm, and D. Savignac, “Optimization of Advanced MOS Technologies for Narrow Distribution of Circuit Performance,” IEEE Trans. CAD/ICAS, Vol. 16, No. 2, pp. 199-204, 1997.2.
  2. K.Yamamoto, M. Tsuno, M. Suga, M. Tanaka, H. Murakami, M. Miura-Mattausch, and M. Hirose, “Velocity overshoot analysis for MOSFETs with channel lengths down to 30nm,” International Conference on Solid State Devices and Materials, 1997.7
  3. 須賀真人, 三浦道子, 小野剛, “ドリフト拡散法及びモンテカルロ法によるシミュレーターを用いた微細MOSFETsの速度オーバーシュートの研究,” 応物支部会 1997, 1997
  4. R. Kakoschke, M. Miura-Mattausch, U. Feldmann, and G. Schraud, “Concurrent Technology, Device, and Circuit Development for EEPROMs,” Proc. Simulation of Semicon. Processes and Devices, pp. 193-196, 1997.9.

1996

  1. M. Miura-Mattausch, U. Feldmann, A. Rahm, M. Bollu, and D. Savignac, “Unified complete MOSFET model for analysis of digital and analog circuits,” IEEE Trans. CAD/ICAS, Vol. 15, No. 1, pp. 1-7, 1996.1.
  2. O. Prigge, M. Miura-Mattausch, D. Savignac, and U. Feldmann, “Worst-case parameters derived from device physics,” Proc. Int. Symp. Circuit and Systems, pp. 1.101-1.104, 1996.6.

1995

  1. U. Feldmann, A. Rahm, and M. Miura-Mattausch, “Benchmarking MOS Transistor Models with Respect to Capacitances and Charges for Analog Applications,” Proc. IEEE Int. Symp. Circuits & Systems, pp. 2.1352-2.1355, 1995.6.
  2. M. Miura-Mattausch, A. Rahm, and O. Prigge, “Influence of analytical MOSFET model quality on analog circuit simulation,” Int. Conf. Simulation of Semiconductor Devices and Processes, Vol. 6, pp. 278-281, 1995.9.

1994

  1. M. Miura-Mattausch, “Analytical MOSFET Model for Quarter Micron Technologies,” IEEE Trans. CAD/ICAS, Vol. 13, No. 5, pp. 610-615, 1994.5.
  2. M. Miura-Mattausch, A. Rahm, M. Bollu, and U. Feldmann, “A novel consistent MOSFET model for CAD application with reduced calculation time,” Proc. Int. Symp. Circuit and Systems, pp. 1.391-1.394, 1994.6.
  3. M. Miura-Mattausch, U. Feldmann, A. Rahm, abd M. Bollu, “Unified complete MOSFET model for analysis of digital and analog circuits,” Proc. IEEE Conf. CAD, pp. 264-267, 1994.11.

1993

  1. M. Miura-Mattausch and W. Bergner, “A new consistent description of MOSFET performance for circuit simulation,” Proc. Int. Workshop VLSI Process and Device Modeling, pp. 134-135, 1993.5.

1992

  1. M. Miura-Mattausch and U. Weinert, “Unified MOSFET model for all channel lengths down to quarter micron,” IEICE Trans. Electron., Vol. E75-C, No. 2, pp. 172-180, 1992.2.

1991

  1. M. Miura-Mattausch and U. Weinert, “Unified MOSFET model for all channel lengths down to quarter micron,” Proc. Int. Workshop VLSI Process and Device Modeling, pp. 98-99, Nara, 1991.5.

1990

  1. M. Miura-Mattausch, J. Ruestig, and R. Kircher, “Dependence of Current Gain on Spacer Geometry and Emitter Size in Polysilicon Self-Aligned Bipolar Transistors,” Solid-State Electronics, Vol. 33, No. 3, pp. 325-331, 1990.3.
  2. M. Miura-Mattausch and H. Jacobs, “Analytical model for circuit saimulation with quarter micron metal oxide semiconductor field effect transistor,” Proc. Europ. Solide State Devices Research Conf., pp. 153-156, 1990.9.
  3. M. Miura-Mattausch and H. Jacobs, “Analytical Model for Circuit Simulation with Quarter Micron Metal Oxide Semiconductor Field Effect Transistors: Subthreshold Characteristics,” Jpn. J. Appl. Phys., Vol. 29, No. 12, pp. L2279-L2282, 1990.12.

1989

  1. J. Fertsch, J. Weng, and M. Miura-Mattausch, “Area-periphery partitioning of current in self-aligned silicon bipolar transistors,” Proc. IEEE Conf. Microelectronic Test Structure, pp. 79-83, 1989.3.
  2. H. Kabza, K. Ehinger, T.F. Meister, H.-W. Meul, P. Weger, I. Kerner, M. Miura-Mattausch, and 9 others, “A 1um polysilicon self-aligning bipolar process for low-power high-speed integrated circuit,” IEEE Electron Device Letters, Vol. 10, No. 8, pp. 344-346, 1989.8.
  3. M. Ohnemus and M. Miura-Mattausch, “Determination of the emitter lateral doping profile for self-aligned bipolar transistors,” Proc. Europ. Solide State Devices Research Conf., pp. 496-499, 1989.9.

1988

  1. K. Ehinger, H. Kabza, J. Weng, M. Miura-Mattausch, I. Maier, H. Schaber and J. Bieger, “Shallow doping profiles for high-speed bipolar transistors,” J. de Physique, Vol. C4, No. 9, pp. 109-112, 1988.9.

1987

  1. M. Miura-Mattausch, A. V. Schwerin, W. Weber, C. Werner, and G. Dorda, “Gtae Currents in Thin Oxide MOSFETs,” IEE Proc., Vol. 134, No. 4, pp. 111-115, 1987.8.
  2. M. Miura-Mattausch, “Current gain dependence on the emitter size of polysilicon-emitter bipoalr transistor,” Proc. Europ. Solide State Devices Research Conf., pp. 637-640, 1987.9.

1986

  1. W. Haensch and M. Miura-Mattausch, “The Hot-Electron Problem in Small Semiconductor Devices,” J. Appl. Phys., Vol. 60, No. 2, pp. 650-656, 1986.7.
  2. 1“Theoretical investigation of impact ionization on silicon in high electric fields,” M. Miura-Mattausch and G. Dorda, Proc. Int. Conf. Physics of Semiconductors, pp. 1303-1306, Stockholm,1986.8.
  3. M. Miura and H. Bilz, “Nonlinear lattice-dynamical theory of mixed-valence compounds,” Solid State Communication, Vol. 59, No. 3, pp. 143-146, 1986.

1985

  1. M. Miura-Mattausch and G. Dorda, “1D analytical treatment of hot-electron effects in short-channel MOSFET,” Physica B, pp. 77-81, 1985.
  2. W. Hansch and M. Miura-Mattausch, “A new current relation for hot electron transport,” Proc. NASECODE, 1985.11.

1984

  1. G. Benedek, M. Miura-Mattausch, W. Kress and H. Bilz, “Anomalies in the surface phonon of TiN (001) ,” Phys. Rev. Letters, Vol. 52, No. 21, pp. 1907-1910, 1984.5.
  2. M. Miura, W. Kress and H. Bilz, “Surface phonon anomalies in superconducting transition metal compounds,” Surface Science, 148, pp. 107-115, 1984.

1983

  1. Y. Sakamoto, M. Miura, K. Hiraga, and H. Murata, “Basic-Potential Method for Studying Crystal Potential,” J. Sci. Hiroshima Univ., Vol. A46, No. 2, pp. 267-336, 1983.1.
  2. A. N. Christensen, W. Kress, M. Miura, and N. Lehner, “Phonon Anomalies in Transition-Metal Nitrides: HfN,” Phys. Rev. B, Vol. 28, No. 2, pp. 977-981, 1983.7.
  3. A. Kida, M. Miura, and H. Murata, “Lattice dynamics of MgO,” Bull. Chem. Soc. Jpn, pp. 2193-2197, 1983.8.
  4. M. Miura, H. Arimori, H. Murata, A. Kida and K. Iishi, “Lattice dynamics of calcium oxide,” J. Phys. Chem. Solids, Vol. 44, No. 7, pp. 627-631, 1983.
  5. K. Iishi, M. Miura, Y. Shiro, and H. Murata, “Lattice dynamics of alpha-quartz including the effect of the width of the atomic electron distribution,” Phys. Chem. Miner., pp. 61-66, 1983.

1982

  1. M. Miura, Y. Sakamoto, H. Murata, and A. Kida, “The Birman pair of basic potentials for evaluating crystal potential energy in an expanse atom approximation,” J. Sci. Hiroshima Univ., Vol. A45, No.3, pp. 419-446, 1982.3.

1981

  1. M. Miura, H. Murata, Y. Shiro, and K. Iishi, “Ionicity scale and piezoelectricity of crystals with zincblende- and wurtzite-type structure,” J. Phys. Chem. Solids, Vol. 42, No. 10, pp. 931-936, 1981

1980

  1. M. Miura, “The Differentiating Feature between the Ⅲ-Ⅴ and the Ⅱ-ⅣCompounds Crystallizing with the Incblende and the Wurtzite Structure,” J. Sci. Hiroshima Univ., Vol.44, No.1, pp.61-81, 1980.7.
  2. M. Miura, Y. Shiro, and H. Murata, “Analysis of the short-range force inluding the r^(-s)-type functional force,” Bull. Chem. Soc. Jpn, Vol. 53, No. 8, pp. 2205-2211, 1980.8.
  3. M. Miura, T. Sato, H. Murata, and Y. Shiro, “Lattice dynamics of wurtzite-type crystlas including the effect of electron extension,” J. Phys. Chem. Solids, 41, pp. 189-197, 1980.

1978

  1. M. Miura, H. Murata, and Y. Shiro, “Lattice dynamics of wurtzite-type crystals-II,” J. Phys. Chem. Solids, Vol. 39, pp. 669-673, 1978.

1977

  1. M. Miura, H. Murata, and Y. Shiro, “Lattice Dynamics of Wurtzite-Type Crystals,” J. Phys. Chem. Solids, Vol. 38, pp. 1071-1074, 1977.